The formation of deep trench capacitors in semiconductor fabrication processes is a complex undertaking that requires many fabrication steps. In fact, there are many challenges in the fabrication of deep trench capacitors such as, for example, lateral undercut in the underlying substrate, as well as issues relating to the formation of the plate.
More specifically, conventional fabrication techniques include a starting structure of a bulk substrate with an oxide layer and SOI (or active) layer bonded to the oxide layer. One challenge in fabricating the deep trenches in such a structure includes lateral undercut into the BOX layer of the SOI substrate that occurs during the deep trench creation process. This lateral undercut has the potential to short the device, e.g., short adjacent deep trenches that are filled with conductor material. For example, in a typical cell layout, trench-to-trench spacing is usually minimized or close to a minimum spacing. If the BOX layer undercut is large, deep trenches may actually short one another as the undercut is filled with conductor, e.g., doped N+ polysilicon. In current technology, this poses a serious problem, especially as the technology scales.
By way of illustration, the lateral undercut occurs due to the etching processes employed to form the deep trenches. For example, etching occurs through the oxide layer and SOI layer and into the bulk substrate. However, due to the complicated etching processes that occurs in at least three different layers, there is a likelihood that lateral undercut in the BOX will occur, thus leading to the shorting.
Also, the undercut can result from plate formation techniques. For example, current technology employs two hydrofluoric (HF) acid etches when using an arsenic-doped glass (ASG) technique to form the plate. In this example, one etch is to remove a hardmask used to open the trenches and which also protects the upper layers of the structure, and a second etch is used to remove arsenic-doped glass (ASG) and its capping layer, e.g., tetraethyl orthosilicate, Si(OC2H5)4 (TEOS). However, these two etching steps have a tendency to etch into the BOX layer forming an undercut. Also, another challenge arises in that the SOI layer must be protected from the arsenic, since the active devices are formed in the SOI layer.
Alternate plate formation techniques pose the same challenges with regard to the SOI layer and lateral undercut issues. In particular, in another plate formation approach, N+ dopants are implanted directly into the substrate from the top of the structure. However, to implant the dopants, it is necessary to protect the SOI layer with a hard mask such as, for example, nitride or oxide. This hard mask adds additional processing steps and costs to the overall fabrication process. Also, as discussed above, the removal of the hardmask results in an additional etching process, which further contributes to the lateral undercut issue.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.